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? semiconductor components industries, llc, 2013 september, 2013 ? rev. 3 1 publication order number: cat93c86b/d cat93c86b 16-kb microwire serial eeprom description the cat93c86b is a 16 ? kb serial eeprom memory device which is configured as either registers of 16 bits (org pin at v cc ) or 8 bits (org pin at gnd). each register can be written (or read) serially by using the di (or do) pin. the cat93c86b features a self ? timed internal write with auto ? clear. on ? chip power ? on reset circuit protects the internal logic against powering up in the wrong state. features ? high speed operation: 4 mhz (5 v), 2 mhz (1.8 v) ? 1.8 v (1.65 v*) to 5.5 v supply voltage range ? selectable x8 or x16 memory organization ? self ? timed write cycle with auto ? clear ? sequential read ? hardware and software write protection ? power ? up inadvertent write protection ? low power cmos technology ? program enable (pe) pin ? 1,000,000 program/erase cycles ? 100 year data retention ? industrial and extended temperature ranges ? 8 ? pin pdip, soic, msop, tssop, 8 ? pad udfn, and wlcsp 6 ? ball packages ? this device is pb ? free, halogen free/bfr free, and rohs compliant ? org do cat93c86b sk gnd v cc figure 1. functional symbol pe cs di *cat93c86bxx ? xxl (t a = ? 20 c to +85 c) ?for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. http://onsemi.com pin configuration do di sk cs 1 see detailed ordering and shipping information in the package dimensions section on page 14 of this data sheet. ordering information soic ? 8 v suffix case 751bd pdip (l), soic (v, x), tssop (y), udfn (hu4), msop (z) pdip ? 8 l suffix case 646aa chip select cs clock input sk serial data input di serial data output do power supply v cc ground gnd function pin name pin function memory organization org program enable pe soic ? 8 x suffix case 751be gnd org pe v cc tssop ? 8 y suffix case 948al udfn ? 8 hu4 suffix case 517az msop ? 8 z suffix case 846ad note: when the org pin is connected to v cc , the x16 organization is selected. when it is connected to ground, the x8 pin is selected. if the org pin is left unconnected, then an internal pull ? up device will select the x16 organization. sk do di gnd vcc cs pin 1 2 1 a b c wlcsp*, ** (c6a) *org internally connected to gnd **pe float wlcsp ? 6 c6a suffix preliminary
cat93c86b http://onsemi.com 2 table 1. absolute maximum ratings parameters ratings units storage temperature ? 65 to +150 c voltage on any pin with respect to ground (note 1) ? 0.5 to +6.5 v stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. 1. the dc input voltage on any pin should not be lower than ? 0.5 v or higher than v cc + 0.5 v. during transitions, the voltage on any pin may undershoot to no less than ? 1.5 v or overshoot to no more than v cc + 1.5 v, for periods of less than 20 ns. table 2. reliability characteristics (note 2) symbol parameter min units n end (note 3) endurance 1,000,000 program / erase cycles t dr data retention 100 years 2. these parameters are tested initially and after a design or process change that affects the parameter according to appropriat e aec ? q100 and jedec test methods. 3. block mode, v cc = 5 v, 25 c. table 3. d.c. operating characteristics (v cc = +1.8 v to +5.5 v, t a = ? 40 c to +125 c, v cc = +1.65 v to +5.5 v, t a = ? 20 c to +85 c unless otherwise specified.) symbol parameter test conditions min max units i cc1 supply current (write) write, v cc = 5.0 v 2 ma i cc2 supply current (read) read, do open, f sk = 2 mhz, v cc = 5.0 v 500 a i sb1 standby current (x8 mode) v in = gnd or v cc cs = gnd, org = gnd t a = ? 40 c to +85 c 2 a t a = ? 40 c to +125 c 5 i sb2 standby current (x16 mode) v in = gnd or v cc cs = gnd, org = float or v cc t a = ? 40 c to +85 c 1 a t a = ? 40 c to +125 c 3 i li input leakage current v in = gnd to v cc t a = ? 40 c to +85 c 1 a t a = ? 40 c to +125 c 2 i lo output leakage current v out = gnd to v cc cs = gnd t a = ? 40 c to +85 c 1 a t a = ? 40 c to +125 c 2 v il1 input low voltage 4.5 v v cc < 5.5 v ? 0.1 0.8 v v ih1 input high voltage 4.5 v v cc < 5.5 v 2 v cc + 1 v v il2 input low voltage 1.65 v v cc < 4.5 v 0 v cc x 0.2 v v ih2 input high voltage 1.65 v v cc < 4.5 v v cc x 0.7 v cc + 1 v v ol1 output low voltage 4.5 v v cc < 5.5 v, i ol = 3 ma 0.4 v v oh1 output high voltage 4.5 v v cc < 5.5 v, i oh = ? 400 a 2.4 v v ol2 output low voltage 1.65 v v cc < 4.5 v, i ol = 1 ma 0.2 v v oh2 output high voltage 1.65 v v cc < 4.5 v, i oh = ? 100 a v cc ? 0.2 v table 4. pin capacitance (note 4) symbol test conditions min typ max units c out output capacitance (do) v out = 0 v 5 pf c in input capacitance (cs, sk, di, org) v in = 0 v 5 pf table 5. power ? up timing (notes 4, 5) symbol parameter max units t pur power ? up to read operation 1 ms t puw power ? up to write operation 1 ms
cat93c86b http://onsemi.com 3 table 6. a.c. test conditions input rise and fall times 50 ns input pulse voltages 0.4 v to 2.4 v 4.5 v v cc 5.5 v timing reference voltages 0.8 v, 2.0 v 4.5 v v cc 5.5 v input pulse voltages 0.2 v cc to 0.7 v cc 1.65 v v cc 4.5 v timing reference voltages 0.5 v cc 1.65 v v cc 4.5 v output load current source i olmax /i ohmax ; cl = 100 pf 4. these parameters are tested initially and after a design or process change that affects the parameter. 5. t pur and t puw are the delays required from the time v cc is stable until the specified operation can be initiated. table 7. a.c. characteristics (v cc = +1.8 v to +5.5 v, t a = ? 40 c to +125 c, v cc = +1.65 v to +5.5 v, t a = ? 20 c to +85 c unless otherwise specified.) symbol parameter v cc < 4.5 v v cc > 4.5 v units min max min max t css cs setup time 50 50 ns t csh cs hold time 0 0 ns t dis di setup time 100 50 ns t dih di hold time 100 50 ns t pd1 output delay to 1 0.25 0.1 s t pd0 output delay to 0 0.25 0.1 s t hz (note 6) output delay to high ? z 100 100 ns t ew program/erase pulse width 5 5 ms t csmin minimum cs low time 0.25 0.1 s t skhi minimum sk high time 0.25 0.1 s t sklow minimum sk low time 0.25 0.1 s t sv output delay to status valid 0.25 0.1 s sk max maximum clock frequency dc 2000 dc 4000 khz 6. this parameter is tested initially and after a design or process change that affects the parameter. table 8. instruction set instruction start bit opcode address data comments x8 x16 x8 x16 read 1 10 a10 ? a0 a9 ? a0 read address an? a0 erase 1 11 a10 ? a0 a9 ? a0 clear address an? a0 write 1 01 a10 ? a0 a9 ? a0 d7 ? d0 d15 ? d0 write address an? a0 ewen 1 00 11xxxxxxxxx 11xxxxxxxx write enable ewds 1 00 00xxxxxxxxx 00xxxxxxxx write disable eral* 1 00 10xxxxxxxxx 10xxxxxxxx clear all addresses wral* 1 00 01xxxxxxxxx 01xxxxxxxx d7 ? d0 d15 ? d0 write all addresses *not available at v cc < 1.8 v
cat93c86b http://onsemi.com 4 device operation the cat93c86b is a 16,384 ? bit nonvolatile memory intended for use with industry standard microprocessors. the cat93c86b can be organized as either registers of 16 bits or 8 bits. when organized as x16, seven 13 ? bit instructions control the reading, writing and erase operations of the device. when organized as x8, seven 14 ? bit instructions control the reading, writing and erase operations of the device. the cat93c86b operates on a single power supply and will generate on chip, the high voltage required during any write operation. instructions, addresses, and write data are clocked into the di pin on the rising edge of the clock (sk). the do pin is normally in a high impedance state except when reading data from the device, or when checking the ready/busy status after a write operation. the ready/busy status can be determined after the start of a write operation by selecting the device (cs high) and polling the do pin; do low indicates that the write operation is not completed, while do high indicates that the device is ready for the next instruction. if necessary, the do pin may be placed back into a high impedance state during chip select by shifting a dummy ?1? into the di pin. the do pin will enter the high impedance state on the falling edge of the clock (sk). placing the do pin into the high impedance state is recommended in applications where the di pin and the do pin are to be tied together to form a common di/o pin. the format for all instructions sent to the device is a logical ?1? start bit, a 2 ? bit (or 4 ? bit) opcode, 10 ? bit address (an additional bit when organized x8) and for write operations a 16 ? bit data field (8 ? bit for x8 organizations). note: the write, erase, write all and erase all instructions require pe = 1. if pe is left floating, 93c86b is in pr ogram enabled mode. for write enable and write disable instruction pe = don?t care. read upon receiving a read command and an address (clocked into the di pin), the do pin of the ca t93c86b will come out of the high impedance state and, after sending an initial dummy zero bit, will begin shifting out the data addressed (msb first). the output data bits will toggle on the rising edge of the sk clock and are stable after the specified time delay (t pd0 or t pd1 ). after the initial data word has been shifted out and cs remains asserted with the sk clock continuing to toggle, the device will automatically increment to the next address and shift out the next data word in a sequential read mode. as long as cs is continuously asserted and sk continues to toggle, the device will keep incrementing to the next address automatically until it reaches to the end of the address space, then loops back to address 0. in the sequential read mode, only the initial data word is preceeded by a dummy zero bit. all subsequent data words will follow without a dummy zero bit. write after receiving a write command, address and the data, the cs (chip select) pin must be deselected for a minimum of t csmin . the falling edge of cs will start the self clocking clear and data store cycle of the memory location specified in the instruction. the clocking of the sk pin is not necessary after the device has entered the self clocking mode. the ready/busy status of the cat93c86b can be determined by selecting the device and polling the do pin. since this device features auto ? clear before write, it is not necessary to erase a memory location before it is written into.
cat93c86b http://onsemi.com 5 figure 2. synchronous data timing sk di cs do valid valid data valid t css t dis t skhi t sklow t dis t dih t csh t csmin t pd0 , t pd1 figure 3. read instruction timing sk cs di do high ? z 11 0 dummy 0 don?t care a n a n ? 1 a 0 address + n d 15 . . . or d 7 . . . address + 2 d 15 . . . d 0 or d 7 . . . d 0 address + 1 d 15 . . . d 0 or d 7 . . . d 0 d 15 . . . d 0 or d 7 . . . d 0 111111111111111 figure 4. write instruction timing sk cs di do standby high ? z high ? z 101 busy ready status t hz t ew t sv verify a n ? 1 a n a 0 d 0 d n t csmin
cat93c86b http://onsemi.com 6 erase upon receiving an erase command and address, the cs (chip select) pin must be deasserted for a minimum of t csmin . the falling edge of cs will start the self clocking clear cycle of the selected memory location. the clocking of the sk pin is not necessary after the device has entered the self clocking mode. the ready/busy status of the cat93c86b can be determined by selecting the device and polling the do pin. once cleared, the content of a cleared location returns to a logical ?1? state. erase/write enable and disable the cat93c86b powers up in the write disable state. any writing after power ? up or after an ewds (write disable) instruction must first be preceded by the ewen (write enable) instruction. once the write instruction is enabled, it will remain enabled until power to the device is removed, or the ewds instruction is sent. the ewds instruction can be used to disable all ca t93c86b write and clear instructions, and will prevent any accidental writing or clearing of the device. data can be read normally from the device regardless of the write enable/disable status. erase all upon receiving an eral command, the cs (chip select) pin must be deselected for a minimum of t csmin . the falling edge of cs will start the self clocking clear cycle of all memory locations in the device. the clocking of the sk pin is not necessary after the device has entered the self clocking mode. the ready/busy status of the cat93c86b can be determined by selecting the device and polling the do pin. once cleared, the contents of all memory bits return to a logical ?1? state. write all upon receiving a wral command and data, the cs (chip select) pin must be deselected for a minimum of t csmin . the falling edge of cs will start the self clocking data write to all memory locations in the device. the clocking of the sk pin is not necessary after the device has entered the self clocking mode. the ready/busy status of the cat93c86b can be determined by selecting the device and polling the do pin. it is not necessary for all memory locations to be cleared before the wral command is executed. figure 5. erase instruction timing sk cs di do standby high ? z high ? z 1 busy ready status 11 verify t hz a n a n ? 1 a 0 t cs t sv t ew
cat93c86b http://onsemi.com 7 package dimensions pdip ? 8, 300 mils case 646aa ? 01 issue a e1 d a l eb b2 a1 a2 e eb c top view side view end view pin # 1 identification notes: (1) all dimensions are in millimeters. (2) complies with jedec ms-001. symbol min nom max a a1 a2 b b2 c d e e1 l 0.38 2.92 0.36 6.10 1.14 0.20 9.02 2.54 bsc 3.30 5.33 4.95 0.56 7.11 1.78 0.36 10.16 eb 7.87 10.92 e 7.62 8.25 2.92 3.80 3.30 0.46 6.35 1.52 0.25 9.27 7.87
cat93c86b http://onsemi.com 8 package dimensions soic 8, 150 mils case 751bd ? 01 issue o e1 e a a1 h l c e b d pin # 1 identification top view side view end view notes: (1) all dimensions are in millimeters. angles in degrees. (2) complies with jedec ms-012. symbol min nom max a a1 b c d e e1 e h 0o 8o 0.10 0.33 0.19 0.25 4.80 5.80 3.80 1.27 bsc 1.75 0.25 0.51 0.25 0.50 5.00 6.20 4.00 l 0.40 1.27 1.35
cat93c86b http://onsemi.com 9 package dimensions soic ? 8, 208 mils case 751be ? 01 issue o e1 eb side view top view e d pin#1 identification end view a1 a l c notes: (1) all dimensions are in millimeters. angles in degrees. (2) complies with eiaj edr-7320. symbol min nom max a a1 b c d e e1 e 0o 8o 0.05 0.36 0.19 5.13 7.75 5.13 1.27 bsc 2.03 0.25 0.48 0.25 5.33 8.26 5.38 l 0.51 0.76
cat93c86b http://onsemi.com 10 package dimensions tssop8, 4.4x3 case 948al ? 01 issue o e1 e a2 a1 e b d c a top view side view end view 1 l1 l notes: (1) all dimensions are in millimeters. angles in degrees. (2) complies with jedec mo-153. symbol min nom max a a1 a2 b c d e e1 e l1 0o 8o l 0.05 0.80 0.19 0.09 0.50 2.90 6.30 4.30 0.65 bsc 1.00 ref 1.20 0.15 1.05 0.30 0.20 0.75 3.10 6.50 4.50 0.90 0.60 3.00 6.40 4.40
cat93c86b http://onsemi.com 11 package dimensions udfn8, 2x3 extended pad case 517az ? 01 issue o 0.065 ref copper exposed e2 d2 l e pin #1 index area pin #1 identification dap size 1.8 x 1.8 detail a d a1 b e a top view side view front view detail a bottom view a3 0.065 ref 0.0 - 0.05 a3 notes: (1) all dimensions are in millimeters. (2) refer jedec mo-236/mo-252. symbol min nom max a 0.45 0.50 0.55 a1 0.00 0.02 0.05 a3 0.127 ref b 0.20 0.25 0.30 d 1.95 2.00 2.05 d2 1.35 1.40 1.45 e 3.00 e2 1.25 1.30 1.35 e 2.95 0.50 ref 3.05 l 0.25 0.30 0.35 a
cat93c86b http://onsemi.com 12 package dimensions msop 8, 3x3 case 846ad ? 01 issue o e1 e a2 a1 e b d c a top view side view end view l1 l2 l detail a detail a notes: (1) all dimensions are in millimeters. angles in degrees. (2) complies with jedec mo-187. symbol min nom max a a1 a2 b c d e e1 e l 0o 6o l2 0.05 0.75 0.22 0.13 0.40 2.90 4.80 2.90 0.65 bsc 0.25 bsc 1.10 0.15 0.95 0.38 0.23 0.80 3.10 5.00 3.10 0.60 3.00 4.90 3.00 l1 0.95 ref 0.10 0.85
cat93c86b http://onsemi.com 13 package dimensions wlcsp 6, 0.96 x 1.17 case tbd issue o
cat93c86b http://onsemi.com 14 ordering information order number specific device marking package type temperature range lead finish shipping cat93c86bli ? g 93c86d pdip ? 8 i = industrial ( ? 40 c to +85 c) nipdau tube, 50 units / tube cat93c86ble ? g 93c86d pdip ? 8 e = extended ( ? 40 c to +125 c) nipdau tube, 50 units / tube cat93c86bvi ? gt3 93c86d soic ? 8, jedec i = industrial ( ? 40 c to +85 c) nipdau tape & reel, 3,000 units / reel cat93c86bvi ? gt3l 93c86d soic ? 8, jedec i = industrial ? 20 c to +85 c nipdau tape & reel, 3,000 units / reel cat93c86bve ? gt3 93c86d soic ? 8, jedec e = extended ( ? 40 c to +125 c) nipdau tape & reel, 3,000 units / reel cat93c86byi ? gt3 m86d tssop ? 8 i = industrial ( ? 40 c to +85 c) nipdau tape & reel, 3,000 units / reel cat93c86byi ? gt3l m86d tssop ? 8 i = industrial ( ? 20 c to +85 c) nipdau tape & reel, 3,000 units / reel cat93c86bye ? gt3 m86d tssop ? 8 e = extended ( ? 40 c to +125 c) nipdau tape & reel, 3,000 units / reel cat93c86bhu4i ? gt3 m4u udfn ? 8 i = industrial ( ? 40 c to +85 c) nipdau tape & reel, 3,000 units / reel cat93c86bhu4e ? gt3 m4u udfn ? 8 e = extended ( ? 40 c to +125 c) nipdau tape & reel, 3,000 units / reel cat93c86bc6atr (note 9) m4 wlcsp ? 6 i = industrial ( ? 40 c to +85 c) snagcu tape & reel, 5,000 units / reel cat93c86bzi ? gt3 m4 msop ? 8 i = industrial ( ? 40 c to +85 c) nipdau tape & reel, 3,000 units / reel cat93c86bze ? gt3 m4 msop ? 8 e = extended ( ? 40 c to +125 c) nipdau tape & reel, 3,000 units / reel cat93c86bxi ? t2 93c86d soic ? 8, eiaj i = industrial ( ? 40 c to +85 c) matte ? tin tape & reel, 2,000 units / reel cat93c86bxe ? t2 93c86d soic ? 8, eiaj e = extended ( ? 40 c to +125 c) matte ? tin tape & reel, 2,000 units / reel 7. all packages are rohs ? compliant (lead ? free, halogen ? free). 8. the standard lead finish is nipdau. 9. preliminary. please contact factory for availability. 10. for additional package and temperature options, please contact your nearest on semiconductor sales office. 11. for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and ree l packaging specifications brochure, brd8011/d. 12. for detailed information and a breakdown of device nomenclature and numbering systems, please see the on semiconductor devic e nomenclature document, tnd310/d, available at www.onsemi.com on semiconductor and are registered trademarks of semiconductor co mponents industries, llc (scillc). scillc owns the rights to a numb er of patents, trademarks, copyrights, trade secrets, and other intellectual property. a list ing of scillc?s product/patent coverage may be accessed at ww w.onsemi.com/site/pdf/patent ? marking.pdf. scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/ or specifications can and do vary in different applications and actual performance may vary over time. all operating parame ters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the right s of others. scillc products are not designed, intended, or a uthorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in whic h the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or us e scillc products for any such unintended or unauthorized appli cation, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unin tended or unauthorized use, even if such claim alleges that scil lc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyrig ht laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5817 ? 1050 cat93c86b/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative

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